The present invention relates generally to semiconductor devices, and more specifically to semiconductor devices that have electrical contacts on opposing external surfaces.
Packaged semiconductor devices typically include a semiconductor die that has integrated circuits formed within, a packaging material that encapsulates the die, and electrically conductive contact leads that connect the die to an external electrical system outside of the packaging material. These packaged devices are connected to the external electrical system by mating one surface of a packaged device with a surface of the external electrical system. However, some types of packaged semiconductor devices, such as packaged semiconductor device 100 as shown in FIG. 1, can be connected to two separate electrical systems by placing an electrical system on the top surface 102 and the bottom surface 104 of device 100. FIG. 1 illustrates a perspective view of a present day semiconductor package 100 wherein molding material 114 is made to be see-through.
Packaged semiconductor device 100 includes a semiconductor die 106, electrically conductive contact leads 108, interconnecting wires 110, uplinking contact leads 112, and a protective molding material 114. Semiconductor die 106 has wirebond pads 116 and uplinking pads 118 formed on the top surface of die 106. Wirebond pads 116 provide a proper surface onto which interconnecting wires 110 are wirebonded to die 106 and uplinking pads 118 provide a proper surface onto which uplinking contact leads 112 can be attached. In one embodiment, wirebond pads 116 are formed of aluminum, uplinking pads 118 are formed of copper, and uplinking contact leads 112 are formed of electrically conductive solder.
Interconnecting wires 110 connect die 106 to contact leads 108, which in turn allow the bottom surface 104 of package 100 to be electrically connected to an electrical system. At the same time, uplinking contact leads 112 allow the top surface 102 of package 100 to be connected to another electrical system. In one implementation, bottom surface 104 can be attached to a printed circuit board and top surface 102 can be connected to an optical device such that the combination of the semiconductor device package 100 and the optical device form an optoelectronic module. For further description relating to semiconductor device package 100, see U.S. Pat. No. 6,364,542, entitled xe2x80x9cDEVICE AND METHOD FOR PROVIDING A TRUE SEMICONDUCTOR DIE TO EXTERNAL FIBER OPTIC CABLE CONNECTION,xe2x80x9d which is incorporated herein by reference.
Semiconductor device package 100 is advantageous because it can be connected to multiple electrical systems. Even though packages such as package 100 are providing useful solutions for computing and electrical systems, improvements to package 100 are still desirable. Several aspects of package 100 require improvement to achieve better structural configurations and to allow more efficient manufacturing steps to be used. For instance, the present manufacturing process is a bit expensive, time consuming, and complex since two different process steps are required to form the two types of contact pads 116 and 118 on die 106. Also, the size of uplinking contacts 112 and the required separation between each forces die 106 to have a relatively large top surface. Therefore, uplinking contacts 112, which are typically solder ball formations, force die 106 to have a larger size than what is actually required to contain the integrated circuits.
Also, during the wafer sorting stage (a wafer testing stage), a testing probe having probes at two height levels is required to make contact with uplinking contacts 112 and wirebond pads 116. Then, during the subsequent package testing stage, the manufacturing tolerances with respect to the process of attaching die 106 into the middle of contact leads 108 becomes critical. This is due to the fact that electrical contact for testing purposes must be made with both the uplinking contacts 112 and contact leads 108. The testing probes for the top and bottom leads are typically in fixed alignment with each other, therefore, die 106 must be in correct alignment with electrical contact leads 108 to allow for proper contact between the probes and the contact leads 108 and the uplinking contacts 112.
In view of the foregoing, a smaller semiconductor device that is easier to manufacture and which has contact surfaces on both a top and a bottom external surface would be desirable.
The present invention is directed to semiconductor device packages that have top and bottom interconnecting surfaces that can be connected to external electrical systems. These packages include internal contact leads that are bent such that they extend from a top surface to a bottom surface of the package and thereby form the corresponding interconnecting surfaces. In some embodiments, a solder ball is formed on either the top or bottom portion of the contact leads so that the solder balls form one of the contact surfaces of the package.
As an apparatus, one embodiment of the present invention includes at least a semiconductor die, a molding material that encapsulates the die, the molding material having a top and a bottom surface, a plurality of electrically conductive bent strips, each bent strip having a first bottom portion that is exposed through the bottom surface of the molding material and a top portion that is exposed through the top surface of the molding material, and a plurality of interconnecting wires that each connect one of the bent strips to the die.
Another embodiment of the apparatus includes at least a semiconductor die, a molding material that encapsulates the die, the molding material having a top and a bottom surface, a plurality of electrically conductive bent strips, each bent strip having a first bottom portion that is exposed through the bottom surface of the molding material and a top portion; a plurality of electrically conductive solder balls that are each attached to the top portion of each bent strip, each solder ball being exposed through the top surface of the molding material, and a plurality of interconnecting wires that each connect one of the bent strips to the die.
In yet another embodiment of the apparatus includes at least a semiconductor die, a molding material that encapsulates the die, the molding material having a top and a bottom surface, a plurality of electrically conductive bent strips, each bent strip having a first bottom portion and a top portion that is exposed through the top surface of the molding material, a plurality of electrically conductive solder balls that are each attached to the bottom portion of at least some of the bent strips, each solder ball being exposed through the bottom surface of the molding material, and a plurality of interconnecting wires that each connect one of the bent strips to the die.
These and other features and advantages of the present invention will be presented in more detail in the following specification of the invention and the accompanying figures, which illustrate by way of example the principles of the invention.